Job Description :
Job Title:Embedded Digital Hardware Design(FPGA development experience in Memory)

Location:San Jose, CA

JD:

Exp : 6-8


EIS : Embedded Digital Hardware Design and Development

5+ years hands-on FPGA development experience in Memory.

Strong logic design background, RTL coding for complex blocks, timing closure in soft fabric, strong experience in ddr protocols.

Quartus or Vivado exp a plus