Job Description :
Top 3 Required Skills:
1. Creatively think and design with Digital Processing Techniques.
2. Design Logic circuits in FPGAs using VHDL or Verilog
3. Effectively communicate their ideas to the his/her team members.

Design digital signal processing (DSP) algorithms that are implemented in a Field Programmable Gate Array.
(Do design using HDL and Matlab programming languages to create electrical circuits arranged to perform complex mathematical functions.
Traditionally Matlab is used to explore solutions and VHDL or Verilog is used to implement a detailed design.
Note DSP is a specific skill set not to be confused with digital ''anythingelse'' )
The biggest challenge is to minimize resources (logic gates, memory, etc) because the components being used have limited resources.
optimizing existing designs will be part of the job and will likely require creative approaches.

Job Description:
Client''s is looking for an experienced Digital Signal Processing (DSP) algorithm design engineer to work on leading edge products.
Engineer will be part of a team implementing direct digital synthesis and digital modulation of packet oriented
data to/from RF transmission mediums using the latest FPGA technologies.
DSP designs are typically architected and modelled in Matlab and/or C, then designed and optimized for implementation in an FPGA.
Developing algorithms to optimize FPGA resources is an important part of the job.
Candidate must also possess circuit design knowledge and be comfortable with RF terms/behaviour.

Key Duties & Responsibilities:
1. Develop DSP algorithms for use in FPGAs.
2. Simulate algorithms with Matlab tools and HDL simulators.
3. Design circuits with Quadrature signals developing modulators using direct digital synthesis and pre-distortion
4. Perform FPGA verification using Questasim, VCS, Riviera or similar simulation tool suite.
Verification tests must be written in an HDL, ''C'' and/or Matlab and run in a self-checking mode.
5. Work with RF design team and trade off digital and analog design issues for optimum designs.
6. Develop and manage verification plans including functional operation, SI verification, timing verification, stress testing,
standards compliance, EMC/EMI compliance, system test.
7. Develop design documentation including; design description, test results, factory test requirements, hardware/software interface, etc.
8. Maintain all design files and supporting files in a source management system.
9. Verify and debug designs in a laboratory environment using spectrum and/or logic analyzers and other test equipment.
10. Assist software development via in-system debugging.
11. Document, debug and fix any problems found.

Expected Skills:
-Experience with DSP filter design including DFT, FFT, FIR or IIR design.
-Be comfortable with communicating in the mathematical lingo of digital signal processing.
-Have VHDL, Verilog, or System Verilog programming and simulation experience.
Having design or verification experience of a medium to large CPLD, ASIC or FPGA device or a major sub-block within a component is a plus.
-Knowledge of general digital circuitry and microprocessors.
-Comfortable using standard lab instruments; meters, oscilloscopes, spectrum analysers, etc.
-Proficient using Windows and/or Unix/Linux computing environments.

Preferred Skills:
Greater than 4 years designing DSP algorithms and 2 or more years modelling and simulating ASICs/FPGAs.

-Experienced Matlab or Labview user.
-Familiarity with OFDM, software defined radio and/or modulator design is a plus.
-Experience with Synopsys or Synplicity synthesis, Altera or Xilinx tool sets.
-Experience working closely with RF circuit designs.
-Scripting skills with perl, python, tcl, shell, or equivalent tools.
-Ability to work independently and strive to innovate.
-Experience with high speed data path and memory interfaces.
-Besides VHDL or Verilog, experience with System Verilog, System C, Vera or the ''e'' language. UVM (Universal
Verification Methodology) experience is a plus.
-Software design experience with C or C++.
-Strong verbal communicator.

Preferred but not required skills:
Experience with System Verilog a plus.
Familiarity with UVM (universal Verification Methodology) would be nice.
Familiarity with Radio Frequency (RF) circuits.

Top 3 Softskills:
Fit into an existing team and work with an existing design.
Be patient and teach team members about DSP concepts.
Be a team player sensitive to previous design approaches and effectively explain trade-offs to sell new ideas

Education & Experience:
Candidates must have one of the following degrees - BSEE/BSEET/BSCS with 6-9 years of technical experience
At least 2 years of DSP design and some experience with ASIC/FPGA design or simulation.