Job Description :
Role: Design Verification Engineer
Location: Bay Area ( Santa Clara,CA and San Jose , CA )
Job Description :
We are looking for ASIC verification engineers with top level DV experience. The candidate will develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment. This includes test plans of complex systems containing multiple state machines and protocol rules.
Experience with verification methodologies such as UVM/VMM/OVM is required, and a strong understanding of UVM is preferred. Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage assertions, preferably using system Verilog. In addition, the following criteria is compulsory for all candidates:
Good understanding of SoC
Prior work experience with DMA on Chip Memory, Verification Methodology
Prior work experience in functional coverage, constrained random on SoC environment
Familiarity with ARM/CPU/GPU/BUS/NOC/Fabric/ clock, rest, Boot etc