Job Description :
Responsibilities:
You will be joining the IT Team for one of the world’s largest semiconductor companies located in the South Bay Area.
You’ll be working with SOC engineers to support and resolve design issues, work on TSMC12/16nm design, PDK support, and building the methodology for verification flow.
Requirements:
5+ years in Analog/Digital Design CAD
Digital design flow from front to back-end
Synopsys (DC, Primetime, ICC2 & StarRCXT), Mentor (Calibre) tool
A script to make design verification flow and programmable skills (Python, Perl, C/C++)
Tool/license installation
Familiarity with TSMC PDK installation and release
Good to have:
Reliability issue (EM/IR)
Ansys Totem/Redhawk flow
DRC/LVS verification
16nm or below design flow
Cadence design flow