Job Description :
Position : ASIC /FGA Verification Engineer ( UVM)

Location : San Jose, CA

Job Type : C2C

Start Date : Immediate & URGENT

Interview: Online coding Skype Video interview followed by customer round.
Face to Face.

Job details :

* This role will require candidates to develop and integrate the current and future RTL designs into a UVM environment.
* Candidates will need to create reports providing coverage and testing results to the teams to help troubleshoot issues in the design.
* This role may also require creating behavioral models of the design and developing RTL which will be integrated into the testing environment.
* Knowledge of Packet Monitoring a plus. Exposure of Verilog and System Verilog