Job Description :
Job overview:
The responsibilities of this position include: UPF based physical synthesis Power content definition using UPF Timing constraints and timing closure Design for test Performing ECO using conformal and Verdi Clock domain crossing check by using Spyglass or 0in RTL lint check

Minimum Qualification:
12+ years industry experience with a minimum 5 years of experience with implementation of complex subsystem with multiple power domains and has experience of at least two tape-out.
Proficient in following tools and flows DC, DCT, or DCG UPF Prime time Timing constraints capture in TCL CLP UPF Clock-domain-crossing It is also
preferred if the candidate has RTL design experience with in-depth knowledge of low power design. Familiar with Verilog and system Verilog.

Required: Bachelor''s, Computer Engineering and/or Electrical Engineering Preferred: Master''s, Electrical Engineering