Job Description :
Hi Team,

Please help me on below requirements to find suitable candidates for my Client.

Physical Designer: Tier 4

Location : Bay Area

Client : Face book

Qualification/Experience/Skills Required
- Hands-on experience performing block level timing closure on advanced FinFET
processes (10nm or newer, TSMC experience preferred)
- Hands-on experience with block level physical design (synthesis to GDS)
- Experience with SoC level integration (multiple blocks, SoC floorplan, clocking and
timing analysis) preferred
- Synopsys (ICC2) and/or Cadence (Innovus) physical design tools
- 5+ years’ industry experience, BS EE
Roles & Responsibilities
- Block level physical design activities for one or more blocks.
- Block level physical design includes floorplan, power plan, placement, CTS, timing
analysis and route.
- Signoff timing and physical verification closure.
- As part of the block level implementation, you will need to ensure the floorplan is
optimal, congestion issues are resolved and timing is under control at every stage from
placement, CTS and route stages.
- Signoff tasks include Timing closure with crosstalk and OCV under Multi-Mode Multi-
corner conditions, Noise signoff with CCS libraries, Physical verification including LVS,
DRC, Antenna and IR closure.
- Own some or all of SoC responsibility including floorplan, clock distribution, power,
reset, timing closure, DFT structures, and on-chip bus/interconnects.