Job Description :
Hi Team,

Trying to fill my Client Face book Positions for below Requirement. Please go through my Job description and Let me know if you have any Suitable profiles.

Verification Engineer: Tier 4

Location : Bay Area

Client : Face book

Qualification/Experience/Skills Required
- Experience with following verification plans at full-chip (SoC) and block levels for
complex designs
- Writing UVM/OVM/VMM and System Verilog tests and coverage metrics for functional
- Hands-on experience with large, automated, metric-driven simulation environments
- Hands-on experience with debug tools, bug tracking and quality metrics and closure
- Synopsys (VCS) and/or Cadence simulation/verification tools
- 5-10 years’ industry experience, BS EE or CE, MS preferred
Roles & Responsibilities
- Under close supervision, assist, research, design, develop and test electronic circuits,
components and chips in CPU, telecommunication, networking, storage and graphic
- Day to day responsibilities for the position includes assisting in creating the verification
plans, creating UVM test bench using latest verification platforms and tools based on
HVL’s and System Verilog or VHDL, assist in developing efficient system/chip level test
and regression environment and run simulation to achieve code and functional coverage
- Develop re-usable test environments, generating test cases and simulations to achieve
code and functional goals, and performing verification design reviews.
- Familiarity/experience with formal verification and/or assertions is a plus.