Job Description :
Senior / Lead RTL Design Engineers
Aricent is a global design and engineering company innovating for the digital era. With more than 12,000 talented designers and engineers and over 25 years of experience, we help the world''s leading companies solve their most important business and technology innovation challenges - from Customer to Chip. Learn more about us at .
Job Description:
5+ years of industry experience in the following areas:
ASIC frontend development.
Logic design, RTL coding, verification, synthesis, and timing closure.
Hardware description languages (Verilog, System Verilog and VHDL
Synopsys DC/PrimeTime or similar tools.
Scripting/programming in C/C++, Tcl, Perl/Csh.
Skill Set & Experience:
Preferred Qualifications: 5+ years of industry experience in 1 or more of the following technical disciplines:
- SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
- RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)
- Low Power Design (clock gating, power gating, power grids, Power Artist, UPF, CPF)
- Networking, Communications (Ethernet (802.11, Wireless LAN 802.11x, Bluetooth, 3G/4G)
- DSP (Filters, Algorithm implementations, MATLAB, modeling)
- Physical Layer Design (USB, HDMI, DDR, MIPI)
- Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop, LNA, OpAmp, ADC-DAC)
Education: BTech/BE/MS - Any Specialization, Electronics/Telecommunication, Electrical) OR (PG – MTech/ME/MS - Any Specialization, Electrical, Electronics/Telecommunication)
Experience (In Month): 65 - 120 months (Experience level – 5 to 12 years)
Location: San Jose, CA USA
Position: Regular – Contracting / Full Time
Engineers Interested can apply and share your resume to
Aricent is an equal opportunity employer.