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Sr. Staff RF Layout Engineer
San Diego, CA
San Diego
CA
92198
Date
: Jun-13-17
2017-06-13
2017-07-13
Sr. Staff RF Layout Engineer
San Diego, CA
Jun-13-17
Work Authorization
US Citizen
GC
H1B
GC EAD
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Senior, Midlevel, Junior
Rate/Salary ($)
:
DOE
Duration
:
6 Month Contract
Sp. Area
:
Others
Sp. Skills
:
Others
Consulting / Contract
CONTRACTOR
Direct Client Requirement
Required Skills
:
Mask Layout, CMOS, IC blocks, RF/analog transceiver CMOS IC
Preferred Skills
:
Domain
:
IT/Software, Financial, Government, HealthCare, Retail, Dot Com, Insurance, Pharmaceuticals, Manufacturing, Telecom
Work Authorization
US Citizen
GC
GC EAD
H1B
Preferred Employment
Corp-Corp
W2-Permanent
W2-Contract
1099-Contract
Contract to Hire
Job Details
Experience
:
Senior, Midlevel, Junior
Rate/Salary ($)
:
DOE
Duration
:
6 Month Contract
Sp. Area
:
Others
Sp. Skills
:
Others
Consulting / Contract
CONTRACTOR
Direct Client Requirement
Required Skills
:
Mask Layout, CMOS, IC blocks, RF/analog transceiver CMOS IC
Preferred Skills
:
Domain
:
IT/Software, Financial, Government, HealthCare, Retail, Dot Com, Insurance, Pharmaceuticals, Manufacturing, Telecom
Intelliswift
Newark, CA
Post Resume to
View Contact Details &
Apply for Job
Job Description
:
RF and Analog Layout Contractor
Duration - 6 Month Contract
Location - San Diego, CA
Overview:
We are seeking a Senior CMOS mask design engineer with RF/analog/mixed-signal IC layout expertise
Work with RF/Analog teams in developing advanced RF/analog transceiver CMOS IC for next generation wireless communications
Drawing of complex layouts of RF/analog cells and blocks for mmWave IC blocks
Skillful in schematic driven layout concept and design constraints
Capable of block and top level floor planning
Qualifications:
Relevant mask design / layout experience from industry
Solid knowledge of TSMC state of the art RF CMOS DRC rules and Pcells
Ability to independently draw and verify complex layouts using Cadence Virtuoso/XL and Caliber DRC/LVS verification tools
Attention to detail, accurate and efficient layout techniques
A good track record of on time work delivery
A self-motivated, team player with good communication skills
Analog layout experience in deep-submicron CMOS is preferred
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