Job Description :
Project Engineer
Location : Chicago, IL
Interview : Phone and F2F or Skype (Preferred Local)
Duration : 6+ Months
JOB DESCRIPTION :
The responsibilities of this position include, but are not limited to, the following:
Layout designs for electronics circuit boards using Cadence Allegro.
Develop and maintain symbol and footprint libraries in Cadence.
Develop and implement high speed design guidelines for devices such as DDR4, PCIe etc.
Develop and implement DRCs (Design Rule Checker) and constraint managers within Cadence
Support schematic design changes
Support PLM (Product life Management) tool development
Interface with outsourced layout work
Manufacturing support for DFM, fabs and assembly
Prepare necessary documentation for high speed layout guidelines, Design Rule Checker, Package generation etc.
Minimum Requirements:
Bachelor degree in Electrical/Electronic Engineering
Experience of schematic and layout using Cadence, Orcad, Allegro toolsets
Experience in high speed digital circuit board design.
Strong verbal and written communications skills.
5-10 years of experience on circuit board layout designs