Job Description :
Position:Design Verification Staff Engineer
Location:Santa Clara, CA
Duration: 6+ months
Note: GC or Citizen or OPT-EAD
We are looking for a contractor to help the Pre-Silicon design verification team in verifying the core-level memory-subsystem blocks. 

The engineer will be responsible for:
1.Developing a test bench (various components, stub model, constrained random test-generator, checkers) for verifying memory-subsystem block. This block is within the CPU core.
2.Verifying the related RTL block using this developed testbench
3.Responsible for coverage for the related block

Minimum Requirements:
1Mandatory) Candidate must have developed at least one test-bench from scratch.
2Mandatory) Candidate must have a solid understanding and hands on experience with System Verilog, uvm, Verilog.
3Highly desirable) Candidate must have worked on verifying one of the following blocks – Level 2 Cache, Load/Store Unit, Data Cache Unit.
4.Candidate should have a good understanding of how CPU core works.
5.Minimum 7-8 years of related work-experience. Preferably Level-17
Update: Resumes submitted so far had no real CPU background - need actual CPU work; no assembly programming background. Need more resumes: Test bench exp, done work with assembly programming/C++