Job Description :
Job Title: Design Verification Engineer
Location: Chandler, Arizona ?
Duration: 12 Months
Skills:
5-7 years of IP, SoC Validation with System Verilog, UVM methodology
AXI-4 expertise, experience in integration and validation with Cadence VIP’s strongly desired.
Experience in writing Systerm Verilog assertions and functional coverage cover-points/groups and analysis.
Proficient in C++
Debug experience using waveforms, timing diagrams and register dumps.
Excellent communication skills (both verbal and written Need to work with remote teams and articulate complex fail scenarios.
Scope The Supplier Engineers are expected to perform following tasks:
Test case development & documentation using standard System Verilog/C++/UVM
Test Env and regression flow updates using Intel flows
Port block level testbench collateral to chip level
Perform verification at SoC in Simulation
Track & improve regression health (pass rates) & coverage