Job Description :
Hi,
We have an opportunity with one of our client for the below requirement, please find the details and revert me back with updated resume.
Role: Verification engineer with Verilog skills OVM and UVM methodology
Location: Folsom, CA
Job Requirement:
In this position, you will be responsible for being a member of a team of verification engineers to verify and deliver world class intellectual property IP to various business groups within Intel. Tasks include writing test plans for functional coverage, defining the architecture of test benches, developing verification methodologies and mentoring verification engineers in the team. You will also be working on DFx validation including test content support for post-silicon teams. You will be required to support the post-silicon teams and mixed signal verification teams for debug of IP level tests in various pre-silicon and post-silicon flows.
Qualifications:
You should possess a Bachelor''s and/or a Master''s degree in Electronics and/or Electronics and Communication and/or Very Large Scale Integration VLSI area. Additional qualifications include: More than 6 years of VLSI Front-end experience a sound understanding of functional verification fundamentals encompassing state machine verification, complex protocol verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows simulations adept in gate level simulations conversant with flows and tools for VLSI logic design and/or functional verification In depth knowledge of System Verilog and verification methodologies like OVM/UVM Working experience on serial/parallel IO/PHYs like DDR/LPDDR, MIPI/D-PHY as well as experience with IEEE JTAG 1149.1 (i.e. TAP interfaces The following qualifications would be added advantages: programming and/or scripting using C++, Perl and others Working knowledge of modern PC architecture and specific IO architecture knowledge is a plus. Experience with DFT scan/atpg is also a plus.